[libre-riscv-dev] [Bug 278] POWER v3.0B spec ambiguity on EXTS and missing EXTZ

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=278

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |programmerjake at gmail.com

--- Comment #1 from Jacob Lifshay <programmerjake at gmail.com> ---
Reply on openpower-hdl-cores:
http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/2020-April/000022.html

On Sat, Apr 4, 2020, 07:16 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> continuing with the implementation of a simulator that is taken
> directly - and literally - from the pseudocode and definitions of
> functions in the spec, we have hit an "inconvenient" definition.
> EXTS, section 1.3.4, page 6:
>
> EXTS(x) Result of extending x on the left with sign
>         bits
>
> the problem is illustrated by asking the very simple question, "how many
> bits?"


Maybe it would work to treat it as a conversion from a bitstring to a
mathematical integer (like a Python3 int) where it can then be converted
back to a bitstring when it is assigned to something with a size again?

You don't need an infinite number of hardware bits to represent the
mathematical integer, since you know the exact range the values fall in so
you can calculate exactly how many bits you need, sign/zero-extending as
needed when converting back to a bitstring.

Jacob

-- 
You are receiving this mail because:
You are on the CC list for the bug.