[libre-riscv-dev] additional ddr3 interfaces

[Luke Kenneth Casson Leighton]

On Wed, Apr 1, 2020 at 1:44 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

> that would be nice, however the t2080 appears to have a 64-bit memory
> interface along with some really high-speed serdes -- both of which will be
> more difficult to achieve.
>
> However, if we get the funding required for the open-source custom DDR3
> interface, we could potentially put two copies on our SoC,

each DDR3/4 RAM interface adds around 0.4 watts per 800mhz clock rate
which, due to power being a square law, ramps up 1.6 watts by 1600mhz.

additionally, they take 150 pins *each* including 20 pins for VDD and GND.

two such high-speed DDR3/4 RAM interfaces not only therefore increases
the power consumption to more than DOUBLE the entire budget allocated
for the SoC, it also puts it into the approx 450-pin category.

with that many pins we might need to use a 0.5 or smaller pitch grid
(otherwise it would be a 20 mm on a side BGA rather than a 15 mm one),
the packaging costs go up, the yields go down...

that said, there's no reason why we can't put the interface on... and
not bring it out....

> which would
> improve GPU performance by a large factor (1.5x?) due to the additional
> memory bandwidth. That would also double the maximum amount of memory we
> could attach to the SoC which is another benefit. If we designed it so it
> would work even with one interface disabled, that would benefit low cost
> applications where the pcb designers don't want to have to pay for two dram
> chips.

four.  designs with only one DRAM chip are extremely rare
(ultra-ultra-low-cost embedded).  typical DRAMs are x16 so you need
two.  smartphones (etc.) typically use special "stacked" ASICs with
eMMC and 1x or 2x 32-bit DRAM interfaces.  they're well north of 250
pins.

> I don't know if we could, but we might be able to sell two different
> variants where one of them has a smaller package where one of the memory
> interfaces is not bonded from the pins to the die, that way, we could save
> money on the chips where both memory interfaces aren't needed without
> needing more than one mask.

yep, that's how it's done.  ST and ATMEL both actually design the
exact same embedded controller for 10 different purposes, some of
which they discover, during testing, that parts of them fail.

all that happens is: they get shoved in a package, sold as lower-cost
items, with the pins not brought out.

it's a really good way to make sure that yields are kept high, nothing wasted.

l.