[libre-riscv-dev] additional ddr3 interfaces

[Jacob Lifshay]

On Tue, Mar 31, 2020, 17:48 Immanuel, Yehowshua U <yimmanuel3 at gatech.edu>
wrote:

> > that would be nice, however the t2080 appears to have a 64-bit memory
> > interface along with some really high-speed serdes -- both of which will
> be
> > more difficult to achieve.
>
> Yes. I was thinking skipping on the SERDES since I personally don’t care
> for PCIE.
> (Its not even remotely Libre).
>
> Unless we want a 10G ethernet, we don’t need high speed SERDES.
>

If we do want to support multi-socket using something like OmniXtend, which
would be amazing but not strictly necessary, 10G ethernet would be
basically required, 1G would work, but would be really slow. We could also
implement something in-between such as 2.5G or 5G.

See http://bugs.libre-riscv.org/show_bug.cgi?id=70 for some previous
discussion.

Using omnixtend allows getting cache coherent memory-mapped i/o over
ethernet (standard ethernet switches work, it can be used simultaneously to
standard tcp/ip), allowing us to easily add custom devices, build giant
numa servers with thousands of cores, add pcie interfaces using a fpga,
interoperate with other processors that support omnixtend, etc.

Also, since it is based on standard ethernet, any computer with an ethernet
port could act as an emulated memory-mapped device or just additional
memory.

>
> > However, if we get the funding required for the open-source custom DDR3
> > interface,
>
> Yup. Working on the funding part at the Create-X angle :)
> Also, it’d be really fascinating if we hear back more from Epic Games.
>

Yay!

Jacob