[libre-riscv-dev] [Bug 272] functions needed in POWER simulator which match 3.0B spec

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=272

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #16)

> Carry-in is addressed in the pseudocode, for instance:
> adde:
> 
> RT <- (RA) + (RB) + CA

oh duh :)

> However, yes we'll probably need to add carry-out handling to the
> SelectableInt class at some point

carry out, yes.

however think ahead to PartitionedSignal.  it becomes more like the unit tests
logic, with multiple incoming carry bits and multiple outgoing carry bits.

this is where it becomes both interesting and also hair-raising to implement
SV.

not least: the regfile gets typecast to a union of arrays of byte, hword, word
and dword.  the "register" RA etc then simply become a pointer to the 64 bit (8
byte) offset into the SRAM of the regfile memory.

but... let's leave that for later :)

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