[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=216

--- Comment #25 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
done.

https://libre-soc.org/3d_gpu/twin_l0_cache_buffer.jpg

the key is that there are only 8 rows (not 16) however each row contains
*two* byte-masks, *two* addr[5:11] and data sets, but *ONE* addr[12:48]
per row.

multiplexing is exclusively limited to 2-in 2-out, on a per-row basis.
each FU having two ports need *only* perform multiplexing on its *own row*
(not to any other rows), using addr[4] to select which bank the two data
sets are to go into.

the thing is that because the two data sets from each FU are consecutive
addresses (one aligned, one mis-aligned, both coming from the exact same
LD/ST), we *know* that they will both go simultaneously into the row:
it's just a matter of which one goes into which row.

so we need a 2-in 2-out crossbar, no multiplexing, no arbitration or
delay-gates needed.

i'll do the writeup now
https://libre-soc.org/3d_gpu/architecture/6600scoreboard/

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