[libre-riscv-dev] additional ddr3 interfaces

[Jacob Lifshay]

On Tue, Mar 31, 2020, 17:23 Immanuel, Yehowshua U <yimmanuel3 at gatech.edu>
wrote:

> > the NEC processors from the powerpc-notebook project *might* be POWER9.
>
> I looked into this - these are actually NXP processors. NXP T2080 to be
> precise.
> The data sheet is a little unhelpful - not making it clear what POWER it
> is.
>
> Anyways - the processor itself has some similarities to our goals. It
> might be a good idea to browse through its specs and see if we can match
> its pinouts down the road. Hopefully, by that time, powerpc-notebook is
> ready to go, and our processor could be just plug and play…
>

that would be nice, however the t2080 appears to have a 64-bit memory
interface along with some really high-speed serdes -- both of which will be
more difficult to achieve.

However, if we get the funding required for the open-source custom DDR3
interface, we could potentially put two copies on our SoC, which would
improve GPU performance by a large factor (1.5x?) due to the additional
memory bandwidth. That would also double the maximum amount of memory we
could attach to the SoC which is another benefit. If we designed it so it
would work even with one interface disabled, that would benefit low cost
applications where the pcb designers don't want to have to pay for two dram
chips. I don't know if we could, but we might be able to sell two different
variants where one of them has a smaller package where one of the memory
interfaces is not bonded from the pins to the die, that way, we could save
money on the chips where both memory interfaces aren't needed without
needing more than one mask.

Jacob