October 2022 Archives by date

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Starting: Sat Oct 1 17:48:27 BST 2022
Ending: Mon Oct 31 22:58:49 GMT 2022
Messages: 102

• [Libre-soc-isa] [Bug 924] potential major opcode allocation for SVP64   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 933] prefix-code (like huffman code) decode/encode instructions   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 933] prefix-code (like huffman code) decode/encode instructions   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 817] Big Integer Math (sv.adde, sv.subfe, sv.madded, 128 by 64-bit -> 64-bit div/rem, maybe more...)   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 817] Big Integer Math (sv.adde, sv.subfe, sv.madded, 128 by 64-bit -> 64-bit div/rem, maybe more...)   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 817] Big Integer Math (sv.adde, sv.subfe, sv.madded, 128 by 64-bit -> 64-bit div/rem, maybe more...)   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 933] prefix-code (like huffman code) decode/encode instructions   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 933] prefix-code (like huffman code) decode/encode instructions   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 933] prefix-code (like huffman code) decode/encode instructions   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 933] prefix-code (like huffman code) decode/encode instructions   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 933] prefix-code (like huffman code) decode/encode instructions   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 905] create Scalar reg access encoding (SVP64-Single)   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 940] New: SVP64 LD/ST auto-increment mode (working with LDST-update)   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 940] SVP64 LD/ST auto-increment mode (working with LDST-update)   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 933] prefix-code (like huffman code) decode/encode instructions   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 905] create Scalar reg access encoding (SVP64-Single)   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 944] New: OPF ISA External RFC ls002 - fmvis and fishmv   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 944] OPF ISA External RFC ls002 - fmvis and fishmv   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 944] OPF ISA External RFC ls002 - fmvis and fishmv   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 817] Big Integer Math (sv.adde, sv.subfe, sv.madded, 128 by 64-bit -> 64-bit div/rem, maybe more...)   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 817] Big Integer Math (sv.adde, sv.subfe, sv.madded, 128 by 64-bit -> 64-bit div/rem, maybe more...)   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 944] OPF ISA External RFC ls002 - fmvis and fishmv   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 650] write rfc for OpenPower fpr <-> gpr moves/conversions   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 944] OPF ISA External RFC ls002 - fmvis and fishmv   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 944] OPF ISA External RFC ls002 - fmvis and fishmv   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 936] change the spec so RC1=1 fail-first instructions always write all outputs up to and including failing subvector   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 940] SVP64 LD/ST auto-increment mode (working with LDST-update)   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 817] Big Integer Math (sv.adde, sv.subfe, sv.madded, 128 by 64-bit -> 64-bit div/rem, maybe more...)   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 817] Big Integer Math (sv.adde, sv.subfe, sv.madded, 128 by 64-bit -> 64-bit div/rem, maybe more...)   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 871] implement pack/unpack mode in ISACaller   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 936] change the spec so RC1=1 fail-first instructions always write all outputs up to and including failing subvector   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 910] mins/maxs with (RB|0) or (RA|0) option?   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 910] mins/maxs with (RB|0) or (RA|0) option?   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 924] potential major opcode allocation for SVP64   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 905] create Scalar reg access encoding (SVP64-Single)   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 924] potential major opcode allocation for SVP64   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 944] OPF ISA External RFC ls002 - fmvis and fishmv   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 936] change the spec so RC1=1 fail-first instructions always write all outputs up to and including failing subvector   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 928] ld/st with shift   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 928] ld/st with shift   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 701] document Matrix, DCT and FFT REMAP in SVP64   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 697] SVP64 Reduce Modes   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 789] svp64 predicate bits and DCT/FFT remap and matrix remap   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 960] New: OPF ISA External RFC ls003 - maddedu and divmod2du   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 960] OPF ISA External RFC ls003 - maddedu and divmod2du   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 960] OPF ISA External RFC ls003 - maddedu and divmod2du   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 960] OPF ISA External RFC ls003 - maddedu and divmod2du   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 960] OPF ISA External RFC ls003 - maddedu and divmod2du   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 960] OPF ISA External RFC ls003 - maddedu and divmod2du   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 960] OPF ISA External RFC ls003 - maddedu and divmod2du   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 960] OPF ISA External RFC ls003 - maddedu and divmod2du   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 962] New: design integer-versions of fft/dct "butterfly" instructions   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 962] design integer-versions of fft/dct "butterfly" instructions   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 933] prefix-code (like huffman code) decode/encode instructions   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 966] New: create shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 966] create shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 966] create shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 966] create shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 968] New: document shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 966] create shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 968] document shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 968] document shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 910] mins/maxs with (RB|0) or (RA|0) option?   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 968] document shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 969] New: 64-bit variants of setvl, svshape, svstep and svindex   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 969] 64-bit variants of setvl, svshape, svstep and svindex   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 969] 64-bit variants of setvl, svshape, svstep and svindex   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 968] document shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 969] 64-bit variants of setvl, svshape, svstep and svindex   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 686] create Power ISA test API   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 686] create Power ISA test API   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 960] OPF ISA External RFC ls003 - maddedu and divmod2du   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 960] OPF ISA External RFC ls003 - maddedu and divmod2du   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 966] create shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 966] create shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 966] create shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 968] document shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 968] document shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 966] create shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 966] create shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 973] New: expand svoffset so it can be used for dynamic vslideup/vslidedown; maybe also add insn for setting it from reg   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 973] expand svoffset so it can be used for dynamic vslideup/vslidedown; maybe also add insn for setting it from reg   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 973] an easy way to shift registers up and down is needed   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 973] an easy way to shift registers up and down is needed   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 973] an easy way to shift registers up and down is needed   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 968] document shift-and-add instruction   bugzilla-daemon at libre-soc.org
• [Libre-soc-isa] [Bug 968] document shift-and-add instruction   bugzilla-daemon at libre-soc.org

Last message date: Mon Oct 31 22:58:49 GMT 2022
Archived on: Mon Oct 31 22:58:49 GMT 2022

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