[Libre-soc-isa] [Bug 966] create shift-and-add instruction

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=966

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
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                 CC|                            |programmerjake at gmail.com

--- Comment #4 from Jacob Lifshay <programmerjake at gmail.com> ---
I'll note the pseudocode is wrong, it should shift left and add, instead it
replaces the lower bits with zero then adds.

https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/bitmanip.mdwn;h=89515ec977385f3ffd7f91b253f795c7d55d69c8;hb=HEAD#l115

 115         case (0): sum[0:XLEN-1] = (n[0:XLEN-1-1] || [0]*1) + (RA)
 116         case (1): sum[0:XLEN-1] = (n[0:XLEN-2-1] || [0]*2) + (RA)
 117         case (2): sum[0:XLEN-1] = (n[0:XLEN-3-1] || [0]*3) + (RA)
 118         default:  sum[0:XLEN-1] = (n[0:XLEN-4-1] || [0]*4) + (RA)

that should be:
case (0): sum[0:XLEN-1] = (n[1:XLEN-1] || [0]*1) + (RA)
and likewise for all other cases.

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