[Libre-soc-isa] [Bug 966] create shift-and-add instruction

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Oct 27 12:16:38 BST 2022


--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #4)
> I'll note the pseudocode is wrong, it should shift left and add, instead it
> replaces the lower bits with zero then adds.

ah well spotted.

> that should be:
> case (0): sum[0:XLEN-1] = (n[1:XLEN-1] || [0]*1) + (RA)
> and likewise for all other cases.

i just realised, it's perfectly fine to do this:

    n <- (RB)
    m <- sm + 1
    RT <- (n[m:XLEN-1] || [0]*m) + (RA)


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