[Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Oct 28 08:32:49 BST 2022


--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #20)

> no, RB and RC are scalar, they can be odd numbered.

doh, forgot.

> > > afaict RS needs to be the lsb bits and RT the msb bits for dsrd,
> > 
> > likely fixed by above, can you confirm?
> i meant that needed to be changed in the unit tests. I fixed the unit tests,
> and replaced scalar RB, RC regs with r3, r5:
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=7d58514beb36c313ccf13a0f14686bd68738f40d

nice. yep makes it clear scalar can be r0-r63.

> (sorry, i just realized i forgot to split out formatting code as a separate
> commit)

doh :)

(In reply to Jacob Lifshay from comment #21)
> it turns out that carrying-4-arg dsld/dsrd don't require extra2-3-2-2
> format.


> i think the experiment is successful, so imho should be merged into
> master. this will resolve my concern in the top comment about dsld/dsrd
> being difficult to use.

excellent, which means they can be added to ls004

> lkcl, what do you think?

yep, unit tests pass, and i've been rebasing regularly.

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