[Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat Oct 22 20:19:51 BST 2022


--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
nope.  if i understand what you want to do it is a *4-in 1-out* operation
which is far too much.  a shift-mask-vector followed by OR-reduction would
do the trick, although the shift-mask-vector ideally needs to be a
3-in 1-out non-immediate version of rldcl:


rldcl2 RA,RS,RB,RC (Rc=0)
rldcl2. RA,RS,RB,RC (Rc=1)


n <- (RB)[XLEN-5:XLEN-1]
r <- ROTL64((RS), n)
b <- (RC)[XLEN-5:XLEN-1]
m <- MASK(b, (XLEN-1))
RA <- r & m

or probably better

m <- MASK(0, b)
RA <- r & m

this does interestingly fall into the bit-extract category, which i added
in bitmanip about... 5 months ago?

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