[Libre-soc-isa] [Bug 817] Big Integer Math (sv.adde, sv.subfe, sv.madded, 128 by 64-bit -> 64-bit div/rem, maybe more...)
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Sun Oct 2 14:31:24 BST 2022
https://bugs.libre-soc.org/show_bug.cgi?id=817
--- Comment #49 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://www.felixcloutier.com/x86/idiv
did some investigation, divmod2du is basically identical to idivq
ELSE IF OperandSize = 64 (* Doublequadword/quadword operation *)
temp := RDX:RAX / SRC; (* Signed division *)
IF (temp > 7FFFFFFFFFFFFFFFH) or (temp < 8000000000000000H)
(* If a positive result is greater than 7FFFFFFFFFFFFFFFH
or a negative result is less than 8000000000000000H *)
THEN
#DE; (* Divide error *)
ELSE
RAX := temp;
RDX := RDE:RAX SignedModulus SRC;
FI;
FI;
which is 3-in, 2-out.
* RDX:RAX is the 128 bit divisor (2 64bit regs)
* SRC is the dividend (1 64bit reg)
* RAX:RDX is the twin div/mod result
dividend[0:(XLEN*2)-1] <- (RC) || (RA)
divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
result <- dividend / divisor
modulo <- dividend % divisor
RT <- result[XLEN:(XLEN*2)-1]
RS <- modulo[XLEN:(XLEN*2)-1]
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