[Libre-soc-isa] [Bug 936] change the spec so RC1=1 fail-first instructions always write all outputs up to and including failing subvector

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Oct 13 08:17:40 BST 2022


--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #0)
> * TODO: add unit tests for RC=1 writing failing subvector with subvl>1

it's not that simple.

the "stop" point will be not only in the middle of an outer
loop, but in the middle of an *inner* loop as well.

do you carry on to the end of the inner loop, long past the initial fail?

where is the state information "fail after the end of something that
happened up to 3 instructions ago?"

what if there is an interrupt in the middle?

how do you know which subvector element was the one that failed,
when all the SVSTATE src/dst steps including substeps have been
reset to zero?

DDFF subvectors are basically not practical.

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