[Libre-soc-isa] [Bug 905] create Scalar reg access encoding (SVP64-Single)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=905

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #13)
> full review needed, answering question:
> 
>     if sv.op RT.scalar RA.scalar RB.scalar is set to "VL=1" is anything lost?
> 
> https://libre-soc.org/openpower/sv/svp64/discussion/

answer is yes: predication "are any bits set" effect on nonzeroing,
has to become "is first bit set" on any "sv.op/pm=xx SCALAR,SCALAR,SCALAR"
operation.

this may not be such a great loss compared to being able to drop
recurring "setvl VL=1" instructions

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