[Libre-soc-isa] [Bug 973] an easy way to shift registers up and down is needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=973

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #2)

> The problem with using twin-predication, is that we would need special
> hardware to recognize those special masks and to optimize it to use
> slideup/down hardware (where elements can be grouped into large chunks),

... and?

that is neither a problem nor is it "our" problem.
it is exactly the kind of thing that goes into
"Architectural Notes", advising implementors to do
precisely and exactly that, should they want high
performance.

failure to provide optimal hardware is not a good
reason to either limit or add further complexity to
an ISA.

SIMD is at the total opposite spectrum of Scalable
Vector ISAs: the entire premise of Scalable Vectors
is precisely that hardware is more intelligent,
where SIMD imposes internal microarchitecture at
the programmer.

but we cannot keep adding more complexity to the REMAP
side of the ISA, it is already causing me some concern.

> rather than general permutation hardware (where each element is processed
> independently -- likely just as slow as svindex).

cyc!ic buffer.  discussed and described many times at least
18 months ago. introduces latency but is far lower cost.
svindex is not "automatically and inherently slow",
i have no idea why you preserve that false notion in
your mind.  it requires extra reads (cached) on the GPR file,
that does not *automatically* make it "slow" under all
possible circumstances and all possible implementations.

> li r3, -1
> sld r3, r3, r4

hmm hmm i thought it would be more complex than that.
the plan/thought was to have general-purpose (RA, RB) direct
access to MASK(), able to specify the start as well
as end.  above is equivalent (i think?) to MASK(0, 63-r4)
is that right?

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