[Libre-soc-isa] [Bug 960] OPF ISA External RFC ls003 - maddedu and divmod2du

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Oct 21 07:53:16 BST 2022


Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
                 CC|                            |programmerjake at gmail.com
             Status|CONFIRMED                   |IN_PROGRESS

--- Comment #2 from Jacob Lifshay <programmerjake at gmail.com> ---

 129 RS is implictly defined as the same register as RC.
 131 *Programmer's Note:
 132 As a Scalar Power ISA operation, like `lq` and `stq`, RS=RT+1.

RS being defined as the same register as RC when non-svp64-prefixed is *not*
how RS is defined currently, currently RS is defined to be RT+1.


If we want to change the definition where RS=RC even without svp64, that's fine
with me, but that should be done everywhere, rather than just in the rfc. Also,
that should have been discussed on the mailing list or bug-tracker (if it was,
sorry i forgot).

If we don't want to change RS=RT+1, then all mentions of RS=RC need to be
deleted from the rfc, except when describing svp64's behavior or if describing
an alternative to what we currently have.

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