[Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=937

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #12)
> rright.  okay. table 13 p1358, Power ISA v3.1, i didn't realise there are
> another 3 columns available (111000, 111001, 111010) as well as four columns
> back on p1353 (010000- 010011)
> 
> therefore yes it's likely ok to use the 111000-111010 group for shift, making
> them 4-arg.

well that went badly.  Vector sv.dsld is required to have the HI-LO source
vector offset by one, pointing to the same vector(+1).  EXTRA2 is incapable
of that.

jacob i have no idea what you need different behaviour in dsld/dsrd for,
so can't begin to go through some options.  what's needed, here?

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