[Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=937

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #0)
> todo list:
> * TODO(programmerjake): resolve difficulty of use issues with dsld/dsrd
> (need splat to RT vector or copy of input as well as a separate scalar shift
> for MSB/LSB word for bigint shift left/right/arithmetic-right) -- something
> more like divmod2du/maddedu with an explicit carrying input/output will
> likely work much better, though requires 4-arg instructions again...

rright.  okay. table 13 p1358, Power ISA v3.1, i didn't realise there are
another 3 columns available (111000, 111001, 111010) as well as four columns
back on p1353 (010000- 010011)

therefore yes it's likely ok to use the 111000-111010 group for shift, making
them 4-arg.

-- 
You are receiving this mail because:
You are on the CC list for the bug.