[Libre-soc-isa] [Bug 944] OPF ISA External RFC ls002 - fmvis and fishmv

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=944

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |programmerjake at gmail.com
             Status|CONFIRMED                   |IN_PROGRESS

--- Comment #1 from Jacob Lifshay <programmerjake at gmail.com> ---
suggestion to use fli2 instead of fishmv and to add fli3-4 to load the rest of
a f64:
https://libre-soc.org/irclog/%23libre-soc.2022-10-07.log.html#t2022-10-07T16:33:27
> fli3: RT <- SINGLE(RT) || imm || [0]*16
> fli4: RT[48:63] <- imm
> so flis; fli2; fli3; fli4 ends up being simply the 4 16-bit quarters
> of the final fp64 in sequence from msb to lsb
> and to do a whole fp64 with ext001 64-bit ops would just be pflis pfli3
> pflis is a whole f32, pfli3 is RT <- SINGLE(RT) || imm[0:31]
<snip>
> i'd like to prioritize instruction names that are easier to understand...
> imho fli2 is quite memorable because it's similar to li
> and it's the second step of loading fp immediates

lkcl mentioned he wanted to prioritize funny mnemonics because he thought they
were more memorable and made better PR.

-- 
You are receiving this mail because:
You are on the CC list for the bug.