[Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=937

--- Comment #19 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #18)

> imho it's not quite right yet, since we have the carrying version, the
> bigint tests need to be:
> sv.dsld *16, *16, 3, 4  # just like sv.maddedu, but shifting
> sv.dsrd/mrr *16, *16, 3, 4  # just like sv.divmod2du, but shifting

with even-numbered RB, yes

> also try signed right shift, where r4 is initialized to repl(msb, 64):
> sradi 4, 18, 63
> sv.dsrd/mrr *16, *16, 3, 4
> 
> afaict RS needs to be the lsb bits and RT the msb bits for dsrd, because if
> you think about it, RS is the carry -- the bits shifted out of the result,
> those bits are shifted right so are at the lsb end.

yep. i'd cut/paste 64-n instead of 128-n which had the effect of
unintentionally swapping RS and RT as the carry-part and result-part...
sort-of.

--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -75,7 +75,7 @@ VA2-Form
 Pseudo-code:

     n <- (RB)[58:63]
-    v <- ROTL128((RA) || [0]*64, 64-n)
+    v <- ROTL128((RA) || [0]*64, 128-n)
     mask <- ¬MASK(n, 63)
     RT <- v[0:63] | ((RC) & mask)
     RS <- v[64:127]

> afaict RS needs to be the lsb bits and RT the msb bits for dsrd,

likely fixed by above, can you confirm?

-- 
You are receiving this mail because:
You are on the CC list for the bug.