[Libre-soc-dev] libre-soc litex sim log

[Luke Kenneth Casson Leighton]

On Friday, August 7, 2020, Jacob Lifshay <programmerjake at gmail.com> wrote:

> On Thu, Aug 6, 2020 at 8:14 AM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> >
> > lkcl at fizzy:~/src/libresoc/soc/src/soc/litex/florent$ ./sim.py
> --cpu=libresoc
>
> I was not able to replicate that on my computer:
>
>
do you have verilator installed?


>   File "/home/jacob/projects/libreriscv/litex/litex/build/
> sim/verilator.py",
> line 211, in build
>     _compile_sim(build_name, verbose)
>   File "/home/jacob/projects/libreriscv/litex/litex/build/
> sim/verilator.py",
> line 150, in _compile_sim
>     raise OSError("Subprocess failed with
>

 i believe you may need to track down the log files created when this
process ran.

it ran one of the Makefiles

l.



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