[Libre-soc-dev] [OpenPOWER-HDL-Cores] libre-soc litex sim log

[Jacob Lifshay]

On Thu, Aug 6, 2020 at 8:14 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> lkcl at fizzy:~/src/libresoc/soc/src/soc/litex/florent$ ./sim.py --cpu=libresoc

I was not able to replicate that on my computer:

...
CC       cmd_litedram.o
 CC       cmd_liteeth.o
 CC       cmd_litesdcard.o
 CC       main.o
 LD       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
python3 -m litex.soc.software.memusage bios.elf
/home/jacob/projects/libreriscv/soc/src/soc/litex/florent/build/sim/software/bios/../include/generated/regions.ld
powerpc64le-linux-gnu

ROM usage: 22.00KiB     (34.38%)
RAM usage: 1.39KiB      (34.77%)

make: Leaving directory
'/home/jacob/projects/libreriscv/soc/src/soc/litex/florent/build/sim/software/bios'
Traceback (most recent call last):
  File "sim.py", line 239, in <module>
    main()
  File "sim.py", line 235, in main
    trace_fst   = 0)
  File "/home/jacob/projects/libreriscv/litex/litex/soc/integration/builder.py",
line 219, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/home/jacob/projects/libreriscv/litex/litex/soc/integration/soc.py",
line 922, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/jacob/projects/libreriscv/litex/litex/build/sim/platform.py",
line 44, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/jacob/projects/libreriscv/litex/litex/build/sim/verilator.py",
line 211, in build
    _compile_sim(build_name, verbose)
  File "/home/jacob/projects/libreriscv/litex/litex/build/sim/verilator.py",
line 150, in _compile_sim
    raise OSError("Subprocess failed with {}\n{}".format(p.returncode,
"\n".join(error_messages)))
OSError: Subprocess failed with 2
make: Entering directory
'/home/jacob/projects/libreriscv/soc/src/soc/litex/florent/build/sim/gateware'
mkdir -p modules
make -C modules -f
/home/jacob/projects/libreriscv/litex/litex/build/sim/core/modules/Makefile
make[1]: Entering directory
'/home/jacob/projects/libreriscv/soc/src/soc/litex/florent/build/sim/gateware/modules'
...

Jacob