[Libre-soc-dev] daily kan-ban update 06AUG2020

[Cole Poirier]

Yesterday:

* MUL unit tests
* Diagram prioritization bug completed for luke to now assess
* Started translation of microwatt mmu.vhdl into soc/src/experiment/mmu.py

I'm definitely misinterpreting some VHDL into incorrect nmigen
structures, but I figured that you can help correct my course here
Luke. I've pasted the whole of mmu.vhdl as comments in mmu.py, and am
translating clause by clause, interleaved with the vhdl comments, into
nmigen. Can I commit this and get some help? I'm about 10-20% through
the process.

Today:

* MUL unit tests
* Recruitment letter
* mmu.py if Luke says it's a good idea

Cole