[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #43 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #42)
> (In reply to Luke Kenneth Casson Leighton from comment #41)
> >
> > why are there 2 power lines? there is only one to the IORef on the STLinkv2.
> > 
> > remember what i said about asking qyestions to which the answer is already
> > deducible?
> 
> Because of the your response in comment #30:

err...

> ```
> > > ```proposed FPGA External Pin to STLINK JTAG pin connecitons
> > >    pin #  | label # | FPGA IO PAD | GPIO # (n/p) | JTAG Pin # (Signal)  |
> > >      1    |  3.3v   |    NONE     |     3v3      |      1 (MCU VDD)     |
> > >      2    |  3.3v   |    NONE     |     3v3      |      2 (MCU VDD)     |
> 
> > good, yes.  the power *from* the ulx3s goes *into* the IO side of the STLinkv2
> > so as to provide the Reference Voltage it needs relative to ulx3s's IO.
> ```
> 
> This led me to believe that both wires were needed.If only one wire is
> needed which one should be connected pin1 or pin2? Does it matter?

*click* right.  ok.  so the answer to that can be deduced from the schematic,
and from the net names.  you'll see that both pin1 and pin2 of that connector,
they're both connected to 3.3v, yes?  so the voltage is going to be the same,
therefore there's no need to connect 2 wires to that same voltage unless there
are two separate locations to put it.

given that the STLinkv2 only has the one input MCU-VDD, you can't put the 2nd
wire anywhere, can you?

the only reason you might want 2 wires is if the current carrying capacity of 1
is too low.  and that's not the case here.

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