[Libre-soc-bugs] [Bug 518] New: Define JTAG pins and set up with litex for versa_ecp5

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=518

            Bug ID: 518
           Summary: Define JTAG pins and set up with litex for versa_ecp5
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: normal
          Priority: Normal
         Component: Source Code
          Assignee: colepoirier at gmail.com
          Reporter: colepoirier at gmail.com
                CC: libre-soc-bugs at lists.libre-soc.org
            Blocks: 383
   NLnet milestone: NLNet.2019.10.Wishbone
    parent task for 383
 budget allocation:

http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html

JTAG pins need to be defined and configured with litex for versa_ecp5


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=383
[Bug 383] Complete first functional POWER9 Core
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