[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #42 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #41)
>
> why are there 2 power lines? there is only one to the IORef on the STLinkv2.
> 
> remember what i said about asking qyestions to which the answer is already
> deducible?

Because of the your response in comment #30:

```
> > ```proposed FPGA External Pin to STLINK JTAG pin connecitons
> >    pin #  | label # | FPGA IO PAD | GPIO # (n/p) | JTAG Pin # (Signal)  |
> >      1    |  3.3v   |    NONE     |     3v3      |      1 (MCU VDD)     |
> >      2    |  3.3v   |    NONE     |     3v3      |      2 (MCU VDD)     |

> good, yes.  the power *from* the ulx3s goes *into* the IO side of the STLinkv2
> so as to provide the Reference Voltage it needs relative to ulx3s's IO.
```

This led me to believe that both wires were needed.If only one wire is needed
which one should be connected pin1 or pin2? Does it matter?

> this needs a wiki page i can't keep track of images here.  and the table too.

Ok will do.

-- 
You are receiving this mail because:
You are on the CC list for the bug.