[Libre-soc-bugs] [Bug 514] review ls180 reset connections

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=514

Staf Verhaegen <staf at fibraservi.eu> changed:

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                 CC|                            |staf at fibraservi.eu

--- Comment #1 from Staf Verhaegen <staf at fibraservi.eu> ---
Another thing to verify is that you don't depend on the verilog initial
section.
A difference between FPGA and ASIC is that most FPGAs embed the initial state
of the registers in their bitstream and on ASIC registers will have a random
value after power-up. Or said otherwise for ASICs setting a value of a register
in the initial section is ignored.

I guess, but am not 100% sure that in nmigen you can only have problems if you
use reset_less signals as you will always assume a reset is applied to an ASIC
after power-up. One of the problems is that pysim has the FPGA behaviour on
reset_less signals and not the ASIC one. That was a few months ago so I don't
know if that has changed. This means that pysim/cxxsim unit tests may not
reveal problems for ASICs with reset_less signals.

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