[Libre-soc-bugs] [Bug 514] review ls180 reset connections

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=514

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #1)

> I guess, but am not 100% sure that in nmigen you can only have problems if
> you use reset_less signals as you will always assume a reset is applied to
> an ASIC after power-up. One of the problems is that pysim has the FPGA
> behaviour on reset_less signals and not the ASIC one. That was a few months
> ago so I don't know if that has changed. This means that pysim/cxxsim unit
> tests may not reveal problems for ASICs with reset_less signals.

litex compiles with verilator, and that runs ok (although i did run into
problems the first time, which i sorted).  i've only used nmigen
reset_less signals where it's known not to matter.

thank you for highlighting this, it'll be something important to check.

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