[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

Staf Verhaegen <staf at fibraservi.eu> changed:

           What    |Removed                     |Added
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                 CC|                            |staf at fibraservi.eu

--- Comment #2 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)

> the arrangement we need is:
> 
> * 64 bits (8 byte) data width
> * byte-level "select" lines
> * 7 bit addressing (128 "rows")
> * 1R *or* 1W (not both)
> * one clock synchronous latency/delay on reads
> 
> i believe this is a "standard" arrangement?

The SRAM will have 1 port that can be used both for read or write with the
following ports:
- a: input of 7 bit
- d: input of 64 bit
- q: output of 64 bit
- we: input of 8 bit
- clk: input of 1 bit

The we vector input will determine for each byte (e.g. 8bits) if it is written
or read.

Suppose we do an operation with 0x000000000000000 stored in an address and with
d equal to 0xFFFFFFFFFFFFFFFF and we equal to 0xF0. After the operation the
address will contain 0xFFFFFFFF00000000 and the Q output will also be
0xFFFFFFFF00000000.

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