[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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    parent task for|                            |199
  budget allocation|                            |
    NLnet milestone|---                         |NLNet.2019.Coriolis2

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Staf we are likely to go with a 1k SRAM block size as the "unit".
this because microwatt is designed around creating multiple independent
SRAM blocks.

Cache Tag RAM widths are very odd amounts: 192 for D-Cache and 184 for I-Cache.
these are better off staying as DFFs.

the arrangement we need is:

* 64 bits (8 byte) data width
* byte-level "select" lines
* 7 bit addressing (128 "rows")
* 1R *or* 1W (not both)
* one clock synchronous latency/delay on reads

i believe this is a "standard" arrangement?

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