[Libre-soc-bugs] [Bug 506] 8x VDD VSS pins needed in ioring

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=506

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #14)

>   I'm still in another meeting... So very quickly and from memory,

ok

>   core2chip is quick helper to avoid manually writing chip and
>   corona netlists. So it allows *only* one pvddeck, pvsseck, pvddick
>   and pvssick.

arg ok. this is what i found.

> To have more, you have to manually edit the chip
>   netlist and add more power pads.

hand-edit autogenerated chip.vst? yuk :)

> Then reload the nestlist
>   along with an updated ioring.py...

yuk :)

i have a feeling that because for ESD only one 3.3v and one 1.8v is possible,
the new domains idea is not going to be useable anyway.

therefore if the current core2chip can be quickly modified to allow N 3.3v vdde
and N 1.8v vddi i think we are good.

except for the PLL i think we just have to put up with one clock, and if no PLL
is ready that one is solved too.

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