[Libre-soc-bugs] [Bug 506] 8x VDD VSS pins needed in ioring

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=506

--- Comment #14 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #12)
> (In reply to Staf Verhaegen from comment #9)
> 
> > So the prototype will have on 3.3V domain and one 1.8V domain.
> 
> rright.  if that's the case - and there is no other option - then there
> is no point doing multiple IO domains at all, we might as well stick
> with the current chip plugin.
> 
> jean-paul i *really* cannot get multiple p_vsseck_0/1 / p_vddeck_0/1 working,
> it is beginning to piss me off.
> 
> can i ask you the favour of modifying experiments4 ioring to show me how
> it is supposed to be done?
> 
> absolutely every single thing that i have tried has failed and i have
> been trying for several weeks.
> 
> add to pads.north fail.
> 
> add to pads.instances fail.
> 
> add vdde fail.
> 
> add p_vddeck_0 fail.  
> 
> add p_vddeck_1 fail.
> 
> 
> if you can add it to experiments4 (which i updated to take pads.instances)
> i can see how it works.

  I'm still in another meeting... So very quickly and from memory,
  core2chip is quick helper to avoid manually writing chip and
  corona netlists. So it allows *only* one pvddeck, pvsseck, pvddick
  and pvssick. To have more, you have to manually edit the chip
  netlist and add more power pads. Then reload the nestlist
  along with an updated ioring.py...

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