[Libre-soc-bugs] [Bug 506] 8x VDD VSS pins needed in ioring

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=506

--- Comment #13 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #11)
> (In reply to Staf Verhaegen from comment #9)
> 
> > FYI, my IO cell library currently won't support different power domains.
> > Although implementation may seem trivial it actually is not. Thing is that
> > you may not fully isolate the domains because then you get ESD problems
> > between pins of different voltage domain.
> 
> is that the case even if there are multiple IO 3.3v domains?

Yes.

> 
> is that related to how close the 3.3v IO power rings are to each other?

No, ESD is small charge but a few kV between any two pins on a chip. Distances
on a chip are never big enough to not having arcs caused by this high voltage.
This means one need to foresee an ESD path between any two pins on a chip to
not have the current flow through unwanted paths.
Typically this is done by sharing the ground between the different domains but
allow the possibility to have different supply voltages. More details I don't
have time to provide now.

> 
> what if the power connection is not a ring, but is instead just a line?

Normally IO cells are arranged in a ring. In theory, you could reduce this to
one line. You can't have multiple disconnected lines.

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