[Libre-soc-bugs] [Bug 506] 8x VDD VSS pins needed in ioring

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=506

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
jean-paul, note especially!

* JTAG will not have a separate p_vdde_jtag / p_vsse_jtag!  its VDDE/VSSE
  should therefore be the "default" (currently p_vddeck_0 / p_vsseck_0)

  however it *does* have a clock entry!

* GPIO *will* have a separate p_vdde_gpio / pvsse_gpio

  however it will *not* have a separate clock entry!  therefore the
  clock should be the "default", set and identified by env.SETCLOCK().

* SDRAM might need two vss/vdd because it is high-speed: p_vdde_sdr_0/1
  and p_vsse_sdr_0/1

  it *does* also have a clock entry in chips['chips.clocks'] dictionary

so there are these four completely separate possibilities:

* no clock domain, no power domain.  default comes from env.SETCLOCK/SETPOWER
* clock domain, no power domain.
* no clock domain, power domain
* clock domain *and* power domain

all external power domain rings will be the 3.3v

all internal (vddi, vssi) however are *one* power domain, but we will need
multiple of them.  these will be 1.8v

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