[Libre-soc-bugs] [Bug 506] 8x VDD VSS pins needed in ioring

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=506

--- Comment #9 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #7)

> my thoughts overnight here are that clock and voltage domains should be part
> of
> the ioring.py "chip" dictionary.
> 
> chip = {'chip.domains': {'SDRAM': ['p_list', 'of', 'iopads', 'for', 'sdram'],
>                          'JTAG': ['p_list', 'of', 'jtag', 'pads']
>                         },
>         'chip.clocks': {'SDRAM': 'p_sdram_clock',
>                         'JTAG': 'p_jtag_tck'
>                         },
>        }

FYI, my IO cell library currently won't support different power domains.
Although implementation may seem trivial it actually is not. Thing is that you
may not fully isolate the domains because then you get ESD problems between
pins of different voltage domain.
So the prototype will have on 3.3V domain and one 1.8V domain.

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