[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #106 from Staf Verhaegen <staf at fibraservi.eu> ---
> >   * vdde / vsse ([e]xternal) for the I/O pads (3.3v in our case)
> 
> out of interest can it go down to 1.8v?

I should be able to go down to 1.8V but I don't currently want to commit to it
for the prototype tape-out.

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