[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #105 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #100)
> > I suppose in the end my IO library will need to be used or does pxlib handle
> > ESD protection and IO voltage level shifting ?
> > What different kind of wiring strategies are you thinking about ?
> > 
> > Also does this need urgent feedback as I would like to first finish the
> > standard cell layout.
> 
>   the pxlib has two power voltages:
> 
>   * vdde / vsse ([e]xternal) for the I/O pads (3.3v in our case)

out of interest can it go down to 1.8v?


>   * vddi / vssi ([i]nternal) for the core.

so it _does_ have level-shifting (because otherwise it would not cope with
the voltage difference between 1.8 and 3.3)


>   By the way, that means that the "outside" must provide both power
>   voltage of 3.3v and 1.8v. Is this the usual way?

yes it is pretty standard.

it is also standard to have not just different voltages (separate IO from
core) it is also standard to:

* have completely different LDO / DCDC PMIC supplies
* have *multiple* IO Voltage domains

this because load and frequency fluctuations can have an adverse impact
on other IO pads running at completely different frequencies.

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