[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #100 from Jean-Paul.Chaput at lip6.fr ---

> I suppose in the end my IO library will need to be used or does pxlib handle
> ESD protection and IO voltage level shifting ?
> What different kind of wiring strategies are you thinking about ?
> 
> Also does this need urgent feedback as I would like to first finish the
> standard cell layout.

  the pxlib has two power voltages:

  * vdde / vsse ([e]xternal) for the I/O pads (3.3v in our case)
  * vddi / vssi ([i]nternal) for the core.

  By the way, that means that the "outside" must provide both power
  voltage of 3.3v and 1.8v. Is this the usual way?

  The input pad have ESD protection.

  But, what we must be sure of, is the interface. If I divert from
  HFNS to chip/corona creation, what's inside the I/O pads is not
  important. From what you (Staf) said, that seems ok, but it would
  be better if you can confirm.

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