[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #99 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #98)

> I suppose in the end my IO library will need to be used or does pxlib handle
> ESD protection and IO voltage level shifting ?

yes, here i ask if it can handle level-shifting.  based on the VST
(public API) it does appear to have external VSS/VDD and internal VSS/VDD,
what we do not know is: what is the range(s) on each.
https://bugs.libre-soc.org/show_bug.cgi?id=506#c5

> What different kind of wiring strategies are you thinking about ?
> 
> Also does this need urgent feedback as I would like to first finish the
> standard cell layout.

jean-paul is in a meeting right now, free in the afternoon. i suspect
that this is coriolis-specific enhancements and that the full pxlib
API will not - in any way - need modification, so you are fine, Staf.

the only thing which would be nice "in the future" (not now) which needs
a modification is some options to set:

* output drive current
* enable/disable pullup/pulldown
* set "mode" (CMOS, TTL i.e. float or "drive-hi + drive-lo")
* enable/disable Schottky / Schmidtt trigger (and its speed) for de-bounce

these are the kinds of sophisticated things that an STM32F or ATSAM has
which make a huge difference to the marketability of an Embedded Controller.

but... definitely not now.  pxlib's API - unmodified - is perfect for this
test ASIC.

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