[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #43 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #42)

> Good catch. I will integrate that, and try to implement a reliable way
> of generating the list.

cool.

> Still working through the placement of the issuer. The placement of the
> IO pins of each block is a lengthy and tedious work... Have to solve
> shortage of length along some sides.


in https://bugs.libre-soc.org/show_bug.cgi?id=199#c35 i described that i
put a prefix in front of names for the operand data, to make that easier.

it should _not_ be laborious, *at all*, to identify the signals.
it should be extremely easy, one line, one pattern.

also: yes as in https://bugs.libre-soc.org/show_bug.cgi?id=199#c35 if you
try to put everything on SOUTH it is pretty much guaranteed not to be
enough space, hence i suggested putting oper_i_* on EAST (or WEST).

for alu0 (and others), the pattern you probably discovered already is:

* oper_i_alu_**** (these are the ones i suggested to bring in on E/W)
* issue_i
* busy_o / done_o
* shadown_i
* rdmaskn
* rd_go / rd_rel
* wr_go / wr_rel
* srcNN_i
* destNN_o and their matching *_ok

please remember: *anything* that is not "convenient" (like this big list
which cannot be easily identified with a couple of wildcard matches, this
means "i got something wrong", ok?


> Hope to have something tomorrow.

feel free to commit regularly even unfinished work for review.  that would
give me a chance to "fix" things that are clearly taking time.

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