[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #42 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #41)
> jean-paul i just checked something to be possible in yosys: to be able
> to flatten individual modules rather than all of it (top).
> 
> this works fine.
> 
> so, to support this: if the YOSYS_FLATTEN can take, instead of a "yes/no"
> (might need a new Makefile parameter, YOSYS_FLATTEN_LIST), the following:
> 
>           YOSYS_FLATTEN_LIST=`cat to_flatten.txt`
> 
> and "to_flatten.txt" to contain at least:
> 
> fast
> cr
> xer
> slow
> int
> pdecode2
> alu0
> branch0
> cr0
> trap0
> ldst0
> 
> and probably many more (basically the list of everything for which a
> top-level
> block is to be written) this will get rid of many of the problems of
> "dangling nets" without having to have a full flatten.
> 
> btw one other way is for that YOSYS_FLATTEN_LIST to be the output from
> a python script that actually notices what's been declared as being
> sub-cells (top level hierarchy) rather than have a separately-maintained
> file that could get out of sync.

Good catch. I will integrate that, and try to implement a reliable way
of generating the list.

Still working through the placement of the issuer. The placement of the
IO pins of each block is a lengthy and tedious work... Have to solve
shortage of length along some sides. Hope to have something tomorrow.

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