[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #44 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit 2c2a9a9ddf07f77ebfb06abb1e7691d462549c19 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Wed Jul 29 16:19:08 2020 +0100

    bit of a big change: add prefixes "cu_" to all CompUnit management signals
    also change go/rel to go_i and rel_o at the same time

i've just sorted that so now e.g. alu0.vst should be more like this:

entity alu0 is
  port ( clk                    : in bit
       ; cu_go_die_i               : in bit
       ; cu_ issue_i                : in bit
       ; oper_i_imm_data_imm_ok : in bit
       ; oper_i_invert_a        : in bit
....
....
       ; rst                    : in bit
       ; cu_shadown_i              : in bit
       ; src3_i                 : in bit
....
       ; cu_busy_o                 : out bit
....
       ; vdd                    : linkage bit
       ; vss                    : linkage bit
       );
end alu0;

so now you should need only these search patterns:

- cu_*
- oper_i_*
- src*_i
- dest*_o
- *_ok

and that should cover everything.  save time! :)



i pushed a new test_issuer.il to experiment9/non_generated

commit 2747314b7ba8cb04f8ca50b1ed016a66831a18b0
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Wed Jul 29 15:20:08 2020 +0000

    updated test_issuer.il to include new names

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