[Libre-soc-bugs] [Bug 412] set up litex for peripherals and linking to core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=412

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
It's possible to avoid the interrupts in a first time, if your CPU wrapper does
not have an interrupt Signal, UART POLLING mode will be used:
https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1063
I'm not sure which platform/target you are using, but you can find a minimal
platform here:
https://github.com/litex-hub/fpga_101/tree/master/lab001
https://github.com/litex-hub/fpga_101/blob/master/lab001/base.py
Or can adapt one of the existing targets.
Regards,
Florent

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