[Libre-soc-bugs] [Bug 412] set up litex for peripherals and linking to core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=412

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
trying this - taken from a random/arbitrary file:

+from migen import ClockDomain
+
 from litex.build.generic_platform import Pins, Subsignal
 from litex.build.sim import SimPlatform
 from litex.build.sim.config import SimConfig
@@ -73,6 +76,12 @@ class SoCSMP(SoCCore):
         self.platform.name = "sim"
         self.add_constant("SIM")

+        self.clock_domains.cd_sys = ClockDomain()
+        self.comb += [
+            self.cd_sys.clk.eq(platform.request("sys_clk")),
+            self.cd_sys.rst.eq(platform.request("sys_rst"))
+        ]
+

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