[Libre-soc-bugs] [Bug 412] set up litex for peripherals and linking to core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=412

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
encountering this error (which was first encountered when using
platform "None", and is coming up again when trying to use platform
"microwatt":

Traceback (most recent call last):
  File "litex/sim.py", line 155, in <module>
    main()
  File "litex/sim.py", line 147, in main
    trace_fst   = 1)
  File "/home/lkcl/src/libresoc/litex/litex/soc/integration/builder.py", line
219, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/home/lkcl/src/libresoc/litex/litex/soc/integration/soc.py", line 922,
in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/lkcl/src/libresoc/litex/litex/build/sim/platform.py", line 44, in
build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/lkcl/src/libresoc/litex/litex/build/sim/verilator.py", line 187,
in build
    platform.finalize(fragment)
  File "/home/lkcl/src/libresoc/litex/litex/build/generic_platform.py", line
314, in finalize
    "No default clock and no clock domain defined")
NotImplementedError: No default clock and no clock domain defined

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