[Libre-soc-bugs] [Bug 412] set up litex for peripherals and linking to core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=412

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
On Wed, Jul 29, 2020 at 12:04 PM Florent Kermarrec
<florent at enjoy-digital.fr> wrote:
>
> Hi,
>
> would you mind sending me the last libre_soc.v file you used for the simulation. I'm having a look at it but just want to use the verilog in a first time and have compilation issues with the first test_issuer.v you provided.

attached.  yes, the first version i found doesn't "start" (remains in
"halted" state).  this one is "up-to-date" with core.py and sim.py.

one thing: do note that we do full 8-bit (byte level) granularity on
the wishbone buses.  i do not know if microwatt does that.

the current bug that i encountered - apart from MEMTEST_BUS_xxx not
being correctly set up for 64-bit - is that if the litex bus is set to
32 bit this _does_ actually work except that the PC is read - even for
an even word - into the *UPPER* 32 bits of the 64-bit Wishbone dat_r,
*not* the lower 32 bits.

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