[Libre-soc-bugs] [Bug 421] TRAP pipeline formal correctness proof needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=421

--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://github.com/antonblanchard/microwatt/blob/master/execute1.vhdl#L478

damn.  completely missed this.  that when SRR1 is written to, bits
in MSR are also changed.  i cut/paste the microwatt code so as to
action it, but missed it

https://bugs.libre-soc.org/show_bug.cgi?id=325#c2

ok give me a mo to update that.

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