[Libre-soc-bugs] [Bug 421] TRAP pipeline formal correctness proof needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=421

--- Comment #21 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Samuel A. Falvo II from comment #19)
> (In reply to Luke Kenneth Casson Leighton from comment #18)
> > https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/trap/formal/
> > proof_main_stage.py;h=48221f2945dd115b31bf34dfc7fb5b3919c1d601;hb=HEAD#l28
> > 
> > should that be +1 on 63-start i.e. 64-start because python slice?
> 
> Yes, thank you.  Good catch.

committed (see comment #20)

> I'm noticing that the trap logic does not drive o.msr.ok; should it? 
> According to the SC pseudo-code, MSR is updated, along with SRR0 and SRR1.

err... err... ah.
https://github.com/antonblanchard/microwatt/blob/master/execute1.vhdl#L621

yep: a trap does not actually modify MSR.  iinteresting.

even for exceptions (which also write NIA and SRR1) they're still not
modifying MSR, it's *SRR1* that contains the modifications (setting
one of the trap bits as defined in section 6.5.9 book III)

if exception occurs write *SRR1*:
https://github.com/antonblanchard/microwatt/blob/master/execute1.vhdl#L1037

how was this not caught by the trap unit test? moo? :)

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