[Libre-soc-bugs] [Bug 421] TRAP pipeline formal correctness proof needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=421

--- Comment #23 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
samuel: you were right, several bits need updating in the MSR.
which *sigh* means it needed first copying.  i'm going to make
some additional changes: move cia and msr into the *input record*
(CompTrapOpSubset in trap_input_record.py) and likewise for
spr_input_record.py

commit d8443042357b41ffaf57f480ff2e1d5b8343c73c (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Tue Jul 21 14:10:54 2020 +0100

    add msr exception bits setting function in hardware
    and do same thing in ISACaller trap

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