[Libre-soc-bugs] [Bug 412] set up litex for peripherals and linking to core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=412

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Created attachment 74
  --> https://bugs.libre-soc.org/attachment.cgi?id=74&action=edit
first version core.py for litex libre-soc

this is a first cut at combining minerva and microwatt to create
a libre-soc litex core.py.  taking minerva i/d cache cpu signal
definitions, widening them to 64 bit, taking microwatt's ppc64le
flags and so on.

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